tl;dr: My tests with AS3340 chips appear to indicate: (1) Pulse width frequency shift is seen with both AS3340 and AS3340A chips; (2) Using a regulated -5V on pin 3 does a good job of suppressing the pulse width frequency shift; capacitor from pin 4 to ground does not work; large resistor between PW CV and pitch CV summing node does work but relies on cancellation and so requires fine tuning; (3) A 10M resistor between pins 4 and 5 suppresses ringing oscillations on the pulse wave falling edge without unacceptably constricting the pulse width range; (4) The value of the pulldown resistor on the pulse wave output is not critical, but should not be too large or too small, and 51k is probably a good value.
I’ve been doing some tests of VCO chips. It’s taken a long time, partly due to my not initially understanding very well how to use these things, and along the way I’ve seen apparent inconsistencies I haven’t fully been able to explain. I can’t be sure the results I have are particularly reproducible, but I don’t want to spend the next month on this, so here’s what I have at this point.
The chips in question are AS3340 and AS3340A from Alfa. They’re Alfa’s version of the Curtis CEM3340, and the AS3340A is supposed to be an improvement over the AS3340 in offering better frequency stability. I have three AS3340As and one AS3340; most of what I’ve done has been with one of the AS3340A chips but I’ve done some checking with the others and gotten similar results.
PWM frequency shift
A known pitfall with the *3340* chips is a pulse width frequency shift. You change the pulse width and the frequency changes. This has been known and discussed for a long time on various forums, with several remedies reported but mostly anecdotally; there’s little I’ve found in the way of good data.
So for example, using the datasheet circuit (but with ±12 V power, and a 680Ω in place of the 620Ω on pin3; HFT was not connected):
|Frequency (Hz)||Frequency (Hz)|
|at 10% PW||at 90% PW||Ratio|
One remedy I’ve seen mentioned is adding a 100 nF capacitor from pin 4 to ground. I didn’t find this to have any effect on the frequency shift. It did mess up the pulse width range, though, and there was weird behavior where if I raised the pulse width from 10% to 90%, after I stopped changing the PW CV the width would slowly continue to increase toward 100% over a period of several seconds!
Sam Battle (LMNC) has tested adding a 20M resistor between the PW CV and the pitch CV summing node. stmllr found they needed a 6.6M resistor to get this to work, and I found in my setup 4.7M largely eliminated the frequency shift.
It’s a simple approach but I have doubts about it. Rather than trying to prevent whatever’s causing the shift, it attempts to cancel the shift out by mixing a little PW CV into the pitch CV. The trouble with that is the size of the shift seems to vary from chip to chip, and it may well be that it varies also depending on the rest of the oscillator circuit and environmental conditions such as temperature. So the amount of cancellation required also varies from setup to setup and maybe from time to time.
It’s been said the shift can be eliminated, or at least mitigated, by using a regulated -5 V at pin 3 instead of -12 V. The idea is that the chip needs a negative voltage in the neighborhood of -5 V, but to accommodate ±12 V or ±15 V power supplies, pin 3 connects to a 7.4 V Zener diode. So you can run that way, or connect -5 V to the pin and not use the Zener.
Here’s what I saw with regulated -5 V:
|Frequency (Hz)||Frequency (Hz)|
|at 10% PW||at 90% PW||Ratio|
Vastly better, and those ratios may be consistent with 1.000 within experimental error. If they’re real, the worst of them corresponds to a pitch shift of about 6.6 cents, audible but barely, and that’s for an extreme change in pulse width.
One thing I noticed was when switching from -12 V to -5 V, the pitch changes (due to the difference between -7.4 V and -5 V), but after the abrupt change the frequency continues to drift for some time before settling down. My guess is this is due to the Zener cooling off, thermally affecting the oscillator.
From Alfa itself comes another recommended fix. It unfortunately calls for a matched transistor pair available only in a surface mount package and a not so commonplace Zener diode. I actually have these parts but haven’t tested this. Given how well the regulated -5 V works, I’m not sure I need to, especially since Alfa recommends using -5 V in any case to “minimize self-heating and improve thermo-stability”.
Something that’s especially evident at low frequency is high frequency oscillations at the falling edge of the pulse wave.
Neither the AS3340 nor the CEM3340 datasheet mentions anything about this, but the CEM3340 datasheet suggests a 1M resistor between pins 4 and 5 to add hysteresis to improve the pulse wave fall time. Other sources recommend a resistor there to cure these oscillations. The Thomas Henry VCO Maximus uses a 1M resistor. The Kassutronics VCO 3340 uses 10M. But what I found was that (1) a 10M resistor (or lower) does indeed suppress the falling edge oscillations
and (2) a resistor also increases the minimum pulse width:
|R (Ω)||Freq (Hz)||Min PW (µS)||Min % width|
A 1M resistor gives next to no PW range at all — and that makes no sense, because Henry uses 1M. This suggests something is wrong in my setup but I can’t find it.
Earlier tests seemed to show 10M was not sufficient to kill the oscillations at ~20 Hz but 3M worked. This also isn’t what I currently see and again I don’t know why.
Pulse wave pulldown
The CEM3340 datasheet specifies a 10k pulldown resistor on pin 4, the pulse wave output. The AS3340 datasheet specifies 51k. LMNC reports using both resistors with both chips and not observing a difference.
What I see is that larger values give longer fall times on the falling edges of the pulse wave (and longer rising edges, but the falling edges are slower). At the high end of audible frequency this makes the wave look severely non-square on the scope when a larger resistance is used. But keep in mind the square edges represent high harmonics which at fundamental frequencies on the order of 10 kHz are too high frequency to be audible. Even 51k probably isn’t large enough to significantly affect the sound of the waveform. Comments in the datasheet suggest there is some benefit in keeping the pulldown current low, so 51k with AS chips seems reasonable.